Methods of forming field oxide and active area regions on a semiconductive substrate

ABSTRACT

Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked by the oxidation mask. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird&#39;s beak region which extends toward the active area. In accordance with a first implementation, a portion of the semiconductive substrate is removed after removal of the oxidation mask but before the formation and removal of a sacrificial oxide layer. In accordance with this implementation, removal of the semiconductive substrate material forms an undercut region under the bird&#39;s beak region which is subsequently filled in with material when the sacrificial oxide layer is formed. In accordance with a second implementation, a portion of the semiconductive substrate is removed after formation and removal of the sacrificial oxide layer. In accordance with this implementation, removal of the semiconductive substrate material forms an undercut region under the bird&#39;s beak region which is subsequently filled in with material when the gate dielectric layer is formed.

RELATED PATENT DATA

This patent application is a continuation resulting from U.S. patentapplication Ser. No. 08/810,336, which was an application filed on Feb.27, 1997, now U.S. Pat. No. 5,897,356.

TECHNICAL FIELD

This invention relates to methods of forming field oxide and adjacentactive area regions on a semiconductive substrate.

BACKGROUND OF THE INVENTION

Integrated circuits are typically fabricated over a semiconductivesubstrate and can include many individual transistor or deviceconstructions. Implementing electrical circuits involves connectingisolated devices through specific electrical paths. It must, therefore,be possible to isolate respective transistor or device constructions. Avariety of techniques have been developed to isolate devices inintegrated circuits. One technique, termed LOCOS isolation (for LOCalOxidation of Silicon) involves the formation of a semi-recessed oxide inthe nonactive (or field) areas of the substrate. Prior art LOCOSisolation is discussed briefly in this section as such pertains to thepresent invention. For a more detailed discussion of LOCOS isolation,the reader is directed to a text by Wolf entitled, "Silicon Processingfor the VLSI Era", Vol. 2, Chapter 2, the disclosure of which is herebyincorporated by reference.

Referring to FIG. 1, a prior art semiconductor wafer fragment in processis indicated generally by reference numeral 10. Such comprises asemiconductive substrate 12 over which a field oxide or isolation oxideregion is to be formed by LOCOS techniques. In the context of thisdocument, the term "semiconductive substrate" is defined to mean anyconstruction comprising semiconductive material, including, but notlimited to bulk semiconductive material such as semiconductive wafer(either along or in assemblies comprising other materials thereon) andsemiconductive material layers (either alone or in assemblies comprisingother materials). The term "substrate" refers to any supportingstructure, including, but not limited to, the semiconductive substratesdescribed above. A pad oxide layer 14 is formed over substrate 12 and anoxidation mask 16, comprises of a suitable material such as siliconnitride, is formed over pad oxide layer 14. Portions of layers 14, 16(not shown) have been removed to expose a substrate portion 18. Portion18 constitutes a portion of the substrate in which a LOCOS isolationstructure or isolation oxide region is to be formed. Adjacent substrateportion 18, a masked substrate portion 20 remains. Portion 20constitutes at least a portion of the substrate which is to support atleast one integrated circuit construction. Accordingly, such portionconstitutes an active area.

Referring to FIG. 2, substrate 12 is exposed to oxidation conditionswhich are sufficient to form oxide isolation region or field oxideregion 22 within portion 18. Accordingly, as is known, the formation ofregion 22 typically causes a bird's beak region 24 to be formed, aportion of which extends under and upwardly lifts oxidation mask 16.

Referring to FIG. 3, oxidation mask 16 and pad oxide layer 14 aresuitably removed or etched. Such defines a more pronounced bird's beakin region 24.

Referring to FIG. 4, a sacrificial oxide layer 26 is formed oversubstrate 12 typically to overcome a phenomena known as the Kooi effect.During the growth of field oxide, the Kooi effect can cause laterdefects when a gate oxide is formed. More specifically, during fieldoxide growth, a thin layer of silicon nitride can form on the siliconsurface and close to the border of the active regions as a result of thereaction between the oxidizing species, oxygen and water, and thesilicon nitride. In particular, NH₃ is generated from the reactionbetween the water and the masking nitride during the field oxidationstep. This NH₃ then diffuses through the oxide and reacts with thesilicon substrate to form silicon-nitride ribbons. When the nitride maskand pad oxide are removed, there is a possibility that thesilicon-nitride ribbon remains present. When gate oxide is subsequentlygrown, the growth rate becomes impeded at the locations where suchsilicon-nitride ribbons remain. The gate oxide is thus thinner at theselocations than elsewhere giving rise to problems associated to lowvoltage breakdown of the gate oxide. The most widely used method ofeliminating the silicon-nitride ribbon problem is to grow a sacrificialoxide layer, typically about 25 to about 50 nanometers thick, afterstripping the masking nitride and pad oxide. This sacrificial oxidelayer is then removed by wet etching before growing the final gateoxide.

It has been found that the removal of the prior formed pad oxide layer14 (FIG. 2) together with the formation and removal of the sacrificialoxide layer 26 can lead to a slightly thinner region 28 adjacent oxideisolation region 22 when the gate oxide layer is ultimately formed.

Referring to FIG. 5, and prior to formation of a gate oxide layer,sacrificial oxide layer 26 is suitably removed. In the illustratedexample, such can cause field oxide region 22 to be recessed to a degreewhich results in the formation of a convex bump 30 laterally adjacentoxide isolation region 22.

Referring to FIG. 6, a gate oxide layer 32 is formed over substrate 12.Oxidation of bump 30 results in localized thinning of the gate oxidewithin region 28. Such thinning can lead to device failure brought on bygate shorting.

This invention arose out of concerns associated with improving theprocessing of semiconductor devices. This invention also arose out ofconcerns associated with improving the uniformity with whichsemiconductor devices can be formed.

SUMMARY OF THE INVENTION

Methods of forming a field oxide region and an adjacent active arearegion are described. A semiconductive substrate is masked with anoxidation mask while an adjacent area of the substrate remains unmaskedby the oxidation mask. The substrate is exposed to conditions effectiveto form a field oxide region in the adjacent area. The field oxideregion has a bird's beak region which extends toward the active area. Inaccordance with a first implementation, a portion of the semiconductivesubstrate is removed after removal of the oxidation mask but before theformation and removal of a sacrificial oxide layer. In accordance withthis implementation, removal of the semiconductive substrate materialforms an undercut region under the bird's beak region which issubsequently filled in with material when the sacrificial oxide layer isformed. In accordance with a second implementation, a portion of thesemiconductive substrate is removed after formation and removal of thesacrificial oxide layer. In accordance with this implementation, removalof the semiconductive substrate material forms an undercut region underthe bird's beak region which is subsequently filled in with materialwhen the gate dielectric layer is formed.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

FIG. 1 is a diagrammatic sectional view of a semiconductor waferfragment at one prior art processing step and is discussed in the"Background of the Invention" section above.

FIG. 2 is a view of the FIG. 1 wafer fragment at a prior art processingstep subsequent to that shown by FIG. 1.

FIG. 3 is a view of the FIG. 1 wafer fragment at a prior art processingstep subsequent to that shown by FIG. 2.

FIG. 4 is a view of the FIG. 1 wafer fragment at a prior art processingstep subsequent to that shown by FIG. 3.

FIG. 5 is a view of the FIG. 1 wafer fragment at a prior art processingstep subsequent to that shown by FIG. 4.

FIG. 6 is a view of the FIG. 1 wafer fragment at a prior art processingstep subsequent to that shown by FIG. 5.

FIG. 7 is a view of a semiconductor wafer fragment at a processing stepwhich corresponds to the FIG. 3 processing step.

FIG. 8 is a view of the FIG. 7 wafer fragment at a subsequent processingstep in accordance a first preferred implementation of the invention.

FIG. 9 is a view of the FIG. 8 wafer fragment at a processing stepsubsequent to that shown by FIG. 8.

FIG. 10 is a view of the FIG. 8 wafer fragment at a processing stepsubsequent to that shown by FIG. 9.

FIG. 11 is a view of the FIG. 8 wafer fragment at a processing stepsubsequent to that shown by FIG. 10.

FIG. 12 is a view of a semiconductor wafer fragment at a processing stepwhich corresponds to the FIG. 5 processing step.

FIG. 13 is a view of the FIG. 12 wafer fragment at a subsequentprocessing step in accordance a second preferred implementation of theinvention.

FIG. 14 is a view of the FIG. 13 wafer fragment at a processing stepsubsequent to that shown by FIG. 13.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws "to promote the progressof science and useful arts" (Article 1, Section 8).

Like numbers from the above-described prior art embodiment are utilizedwhere appropriate, with differences being indicated with the suffix "a"or with different numerals. Processing of the below-describedsemiconductor wafer fragment takes place in accordance with the abovedescribed methodology up to and including that which is shown in FIG. 3.It is at this point that the inventive departures begin.

Referring to FIG. 7, a portion of a semiconductor wafer fragment inprocess is indicated generally at 10a. Such includes a semiconductivesubstrate 12a. The FIG. 7 construction is one which corresponds to theFIG. 3 construction which, as discussed above, constitutes a waferfragment after removal of the pad oxide layer 26. It is of coursepossible, however, for a pad oxide layer not to be used. In such case,the FIG. 7 construction would constitute a wafer fragment after removalof an oxidation mask such as mask 16 in FIG. 2. Accordingly, a substrateportion 20a constitutes an active area portion which was previouslymasked with an oxidation mask similar to that which is shown at 16 inFIG. 2. Substrate portion 18a constitutes an adjacent area of thesemiconductive substrate which was not previously masked with anoxidation mask during which time a field oxide or oxide isolation region22a was formed. Accordingly during such processing, a bird's beak region24a was formed to extend toward active area portion 20a. Oxide isolationregion 22a, and more specifically bird's beak region 24a, includes aterminus 25 disposed laterally adjacent and joining with active areaportion 20a. The joinder of terminus 25 with active area portion 20adefines surface at a first elevation indicated at E₁.

Referring to FIG. 8, and in accordance with a first preferredimplementation, material of semiconductive substrate 12a is removed toform an outer conductive substrate surface 15 at a second elevation E₂which is lower than or below first elevation E₁. As shown, the removingof the substrate material is conducted with field oxide region 22a andactive area portion 20a being outwardly exposed. In accordance with oneaspect of the invention, semiconductive substrate material is removedproximate terminus 25 and to a degree which is sufficient to undercut atleast a portion of the bird's beak defining bird's beak region 24a. Theremoval of such substrate material forms, in the illustrated andpreferred embodiment, a slot 33 between isolation region terminus 25 andunderlying semiconductive material of substrate 12a. Preferably, thesemiconductive substrate material is chemical etched substantiallyselective relative to the field oxide region to suitably form slot 33without appreciably etching terminus 25 or the bird's beak. Such etchingis preferably accomplished in the absence of any photoresist over thefield oxide region or substrate active area. An exemplary etch chemistryincludes dilute ammonium hydroxide (NH₄ OH) or a mixture of NH₄ OH andhydrogen peroxide (H₂ O₂).

Referring to FIG. 9, substrate 12a is subjected to oxidizing conditionswhich are effective to form a sacrificial oxide layer 26a over substrateactive area 20a. At the same time, slot 33 is filled with insulativematerial which constitutes a portion of the sacrificial oxide layer.Such oxidizing conditions permit the growth of oxide insulative materialto replace at least some of the semiconductive material which was etchedaway under terminus 25.

Referring to FIG. 10, sacrificial oxide layer 26a is removed orotherwise stripped as by suitable etching from over active area portion20a. Accordingly, a generally planar substrate surface 35 is outwardlyexposed and displays little, if any, of the above-described convex bump30 (FIG. 5).

Referring to FIG. 11, a gate dielectric layer 37 is formed over activearea portion 20a. Further processing of wafer fragment 10a can takeplace in accordance with known processing techniques.

The above described implementation is one which constitutes removing aportion of the semiconductive substrate after the removal of theoxidation mask and pad oxide layer (in the event a pad oxide layer iseven utilized), but before the formation and removal of the sacrificialoxide layer. In accordance with this implementation, removal of thesemiconductive substrate material forms an undercut region which issubsequently filled in with material when the sacrificial oxide layer isformed. In the event a sacrificial oxide layer is not utilized, theundercut region will be filled in with material when the gate dielectriclayer is formed.

Referring to FIG. 12, a second preferred implementation is set forth.Like numbers from the above-described prior art and inventiveembodiments are utilized where appropriate, with differences beingindicated with the suffix "b" or with different numerals. The startingpoint for the discussion immediately below corresponds to the FIG. 5construction which is after the sacrificial oxide layer has been formedand removed. To that extent, processing of the illustrated FIG. 12 waferfragment takes place in accordance with the above described processingrelative to FIGS. 1-5. Accordingly, such results in the formation of aconvex bump 30b of material within active area portion 20b proximate thefield oxide region 22b.

Referring to FIG. 13, and following the removal of the sacrificial oxidelayer, material of substrate 12b in active area portion 20b is removedto provide a substantially planar substrate surface 39 within activearea portion 20b. As shown, at least some and preferably all of convexbump 30b is removed during the removal of the semiconductive substratematerial. In the illustrated and preferred embodiment, substratematerial is chemical etched substantially selective relative to thematerial which constitutes oxide isolation region 22b. Such preferablydoes not appreciably etch the bird's beak region or terminus 25. Suchpreferred etching forms an outer semiconductive substrate surface at asecond elevation E_(2b) which is below first elevation E₁ (whichcorresponds to the point at which terminus 25 joins active area portion20a).

Referring to FIG. 14, substrate 12b is subjected to conditions which aresufficient to form or grow gate dielectric layer 37b. As shown, thesubstrate material which was previously removed is replaced withinsulative gate dielectric material.

The second described implementation is one which constitutes removing aportion of the semiconductive substrate after formation and removal ofthe sacrificial oxide layer. In accordance with this implementation,removal of the semiconductive substrate material forms an undercutregion which is subsequently filled in with material when the gatedielectric layer is formed.

Either of the above described implementations can provide a gatedielectric layer which is more uniform in elevational thickness. Suchstems from the fact that the above described methodology reduces if noteliminates either (1) the propensity of the convex bump to form (thefirst described implementation), or (2) the convex bump once formed (thesecond described implementation) proximate the joinder region of theisolation oxide and the substrate active area.

In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood, however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

I claim:
 1. A method of forming a substrate active area adjacent anoxide isolation region comprising:forming an oxide isolation region overa semiconductive substrate proximate a semiconductive substrate activearea, the isolation region having a portion extending to the activearea; after forming the oxide isolation region, removing material of thesemiconductive substrate of the active area to a degree sufficient toform a slot between the isolation region portion and underlyingsemiconductive material; and filling the slot with insulative material.